1. Technical Field
The present invention relates in general to clock translators and in particular to clock translators for microprocessors. Still more particularly, the present invention relates to non-integer multiple clock translators for microprocessors.
2. Description of the Related Art
In modern personal computers (PCs), PC computer boards typically have a transmission speed limitation that is less than the PC's microprocessor speed. Cost considerations have prevented the PC board from being made faster. Instead, the speed of the PC computer system has been increased by speeding up the microprocessor and providing internal cache memory to the processor, decreasing the bandwidth required of the system bus. Thus, data being transferred over the bus on the PC computer board is timed by a bus clock having a speed limitation of, for example, 66 Mhz, while the processor is operating at a speed of, for example, 100 Mhz. Data being transferred from the PC board to the microprocessor would be delivered to a clock translator that synchronizes data from the bus with the faster processor clock and transfers it out to the processor. Therefore, in order to couple the faster processor with the slower PC board, the external clock on the PC board has to be synchronized with the internal system clock on the microprocessor.
In the prior art, the processor clock has typically been an integer (n) multiple of the external clock, typically two or three times faster. While the prior art has provided clock translators for operation with internal microprocessors that operate at nx integer multiples of the system bus speed, the prior art has heretofore not provided a clock translator capable of operating with a system microprocessor that operates at both an integer and a non-integer multiple of clock frequencies. Thus, it would be desirable to provide a multiple clock translator that translates data to a non-integer multiple clock frequency.